Hardware
Processors, NPUs and accelerators built for inference at the edge
Edge AI chips run neural network inference close to the sensor, inside a device or on a factory floor, instead of in a remote data centre. This category covers systems-on-chip, neural processing units, vision processors and discrete accelerator modules.
Representative platforms with the details engineering and procurement teams shortlist on.
Entry-level Jetson developer kit rated at up to 67 INT8 TOPS for compact robots, cameras and vision gateways.
Flagship Orin-generation module rated at up to 275 INT8 TOPS with 64 GB of memory for multi-sensor autonomous machines.
Discrete 26 TOPS INT8 inference processor supplied as a chip or M.2 module to add vision analytics to an existing system.
Generative-capable M.2 accelerator rated at 40 INT4 TOPS with its own LPDDR4 memory and 2.5 W typical power.
Low-power 4 TOPS Edge TPU module rated at 2 TOPS per watt for small, always-on inference workloads.
Embedded vision SoC with an 8 TOPS deep learning accelerator, dual Cortex-A72 cores and a hardware imaging pipeline.
Eight-core application processor with a 6 TOPS INT8 NPU and 8K video encode and decode, widely used in edge video devices.
Specifications are summarised from publicly published manufacturer material and are provided for orientation only. Always confirm current figures directly with the manufacturer before purchasing or designing in.
Chip manufacturer
Develops the Jetson family of edge system-on-modules, the DGX Spark desktop AI system and the JetPack, TensorRT and DeepStream software stacks used for edge inference, robotics and vision AI.
Santa Clara, California, United States
Chip manufacturer
Supplies Core Ultra client processors that combine CPU, Arc graphics and an integrated NPU, and maintains the open-source OpenVINO toolkit for optimising inference on Intel CPUs, GPUs and NPUs.
Santa Clara, California, United States
Chip manufacturer
Designs the Snapdragon X platform for Windows PCs and edge clients, pairing Oryon CPU cores, Adreno graphics and the Hexagon NPU. Qualcomm also owns the Edge Impulse edge MLOps platform.
San Diego, California, United States
Chip manufacturer
Produces Ryzen AI processors that combine Zen 5 CPU cores, RDNA 3.5 graphics and the XDNA 2 NPU, with large unified memory configurations used for local generative AI workloads.
Santa Clara, California, United States
Chip manufacturer
Publishes the Coral Edge TPU accelerators for low-power on-device inference and maintains LiteRT, the on-device runtime that succeeded TensorFlow Lite, together with the open-weight Gemma model family.
Mountain View, California, United States
Chip manufacturer
Supplies the AM6xA and TDA4 processor families, which combine Arm application cores, vision and imaging accelerators and a deep learning accelerator for embedded vision, robotics and automotive designs.
Dallas, Texas, United States
Chip manufacturer
Fabless SoC designer whose RK35xx application processors combine Arm CPU clusters, Mali graphics and an integrated NPU, widely used in single-board computers, panel devices and edge video products.
Fuzhou, China
Edge AI startup
Fabless company developing discrete edge AI processors, M.2 and PCIe accelerator modules and the Hailo AI Software Suite, spanning classic vision workloads and, with Hailo-10H, generative models.
Tel Aviv, Israel
Chip manufacturer
Produces the IMX500 intelligent vision sensor, a stacked CMOS image sensor with an integrated AI processing block and on-chip memory, supported by the AITRIOS edge AI sensing platform.
Atsugi, Kanagawa, Japan